Photolithographic image formation in a photosensitive polymer layer followed by plasma-based transfer of the defined photo resist patterns into other materials has been remarkably successful in enabling the production of micro- and nanometer-scale electronic features. This has required a continuous evolution of materials and patterning techniques such as photolithography systems, photo-polymer resists, and etching equipment and processes.
For patterned structures, the critical dimension (CD) relates to the width of the patterned structures, e.g. patterned lines. The variation of the line width is expressed by the Line Width Roughness (LWR) value. The variation of the edges of the line with respect to an ideal case is expressed as Line Edge Roughness (LER). In optical lithography the following correlation is generally used between LWR and LER:σLWR=21/2*σLER;wherein σ denotes standard deviation.
The manufacturing of sub-20 nm technologies has triggered a radical change in photo resist-materials; consequently, this technology has to face many new challenges such as controlling line width and line edge roughness (LWR and LER). Effects of line width roughness and line edge roughness become more important as feature dimensions become smaller, which makes the control of LWR and LER a major scaling concern. This line width roughness, defined as the 3σ critical dimension (CD) variation along a segment of a line, is having a big impact on the transistor performance. In addition, increased LWR also induces higher variance in device performance which can affect circuit stability. Given the 10% gate CD criterion, devices fabricated with the 20 nm node technology are required to have a maximum allowable LWR which is smaller than or equal to 2 nm, or even smaller than or equal to 1 nm. The current best LWR that can be achieved in photo resist using EUV lithography is about 3 to 4 nm. A substantial improvement in LWR of the patterned structures is required to minimize the impact on device performance.
Self-Aligned Double (or Multiple) Patterning (SAD(M)P) using 193 nm immersion lithography also suffer from high LWR and LER values after lithography development.
A plasma treatment may be applied using HBr or H2 plasma on patterned photo resist features for smoothening of these photo resist features in an effort to reduce LWR/LER. However, this approach introduces an additional plasma step into the process flow.
There exists a need for novel techniques which allow to further reduce LWR and LER, especially for sub-20 nm technologies.